1. Field of the Invention
The present invention relates to an MOS semiconductor device such as an MOSFET (an insulated gate field effect transistor).
2. Description of the Background Art
For the purpose of lowering on-resistance (Ron), an MOSFET is such that a surface cell pattern (101 and 102) including an MOS structure is being more and more miniaturized, such as from FIG. 13A to FIG. 13B, in accordance with the energy saving trend in the world. FIG. 2 shows an enlarged sectional view of a ½ pitch size of the cell pattern 101 shown by the dotted frame of FIG. 13A, and FIG. 3 shows an enlarged sectional view of a ½ pitch size of the cell pattern 102 shown by the dotted frame of FIG. 13B. A cell pitch b is smaller than a cell pitch a. Consequently, a channel length L2 of the MOS structure of the cell pitch b is shorter than a channel length L1 of the MOS structure of the cell pitch a, meaning that it is possible to make the on-resistance of the MOSFET of FIG. 13B lower than that of the MOSFET of FIG. 13A.
On-resistance (Ron), which is of important characteristics of an MOSFET, is roughly separated into three resistance components; Rch (channel resistance), Rjfet (resistance based on a junction FET), and Repi (the resistance of an n-type drift layer 2 formed by an epitaxial growth), as shown by a main portion sectional view of an MOSFET in FIG. 12. That is, one is the Rch which is the resistance component of each n channel 5 of the MOS structure. Another is the Rjfet which is the resistance of a surface layer of the n-type drift layer 2 sandwiched between adjacent p-type body regions 3. Still another is the Repi which is the resistance of the n-type drift layer 2 depending on a breakdown voltage. Also, the Rjfet and Repi are determined in conjunction with a quasi-plane-junction shape too. A description will be given of a heretofore known method as a method of lowering each on-resistance (Ron) component.
A method of reducing a channel length L by miniaturizing the cell pattern, as previously described, an increase of a series of circuits by a reduction in cell pitch, and the like, are well-known general methods of lowering the Rch (channel resistance).
A method, such as an optimization of the impurity concentration in a width BL of a junction FET region (between the p-type body regions 3) or an increase of a series of circuits by a reduction in cell pitch, is carried out in order to lower the Rjfet (resistance based on the junction FET). The miniaturization of the cell pattern relates to any of the methods.
There is the following method of lowering the Repi (resistance of the n-type drift layer 2). The p-type body regions 3 are densely disposed to make a nearly planar quasi-plane junction. The junction surface of the p-type body regions 3 is sufficiently approximated to the original plane junction by this quasi-plane junction, and thus formed into a nearly planar waved shape. By so doing, it is possible to increase a breakdown voltage determined by the shape of a pn junction surface to a value close to that of a theoretical breakdown voltage resulting from the plane junction. Heretofore, a high breakdown voltage has been maintained by making the specific resistance of the n-type drift layer 2 higher than a specific resistance value at which the theoretical breakdown voltage can be obtained, and thus sacrificing the on-resistance. However, it is possible to lower the specific resistance at the same breakdown voltage by making the pn junction of the p-type body regions 3 to be the quasi-plane junction, as a result of which it is possible to lower the resistance component (Repi) of the n-type drift layer 2.
The cell pattern miniaturization is usually carried out for lowering any of the three resistance components. The previously described miniaturization of the cell pattern of the heretofore known MOSFET from FIG. 13A to FIG. 13B also conforms with this flow.
It is known that there exist the following kinds of documents relating to this kind of miniaturization of the cell pattern of the MOSFET, a decrease in the on-resistance (Ron), and an improvement of an SOA. With regard to an insulated gate bipolar transistor (IGBT) device, there is described a method of improving an SOA by increasing a channel length (L) (increasing the Rch) (JP-A-2001-24184). Also, with regard to a device relating to an IGBT in the same way, there is described a non-linear channel shape wherein a planar portion of an n channel and an n channel in the vertical portion of a sidewall of a gate trench are combined together (JP-A-2010-272741). Furthermore, as a solution to the problem that a trade-off between the previously described on-resistance (Ron) and SOA becomes obvious, it is described that a channel conductance Gd is lowered by changing gate threshold voltages (Vth) of the respective opposed channels in the p-type body regions 3 (JP-T-2004-511084(the term “JP-T” as used herein means a published Japanese translation of a PCT patent application)). Also, there is a document in which is described a technology of miniaturizing the cell pattern of a planar MOSFET (JP-A-2003-008014). There is also a document in which is described a technology relating to a shallow trench (JP-A-8-236766).
However, the MOSFET whose cell structure is miniaturized for the purpose of lowering the on-resistance (Ron) is such that there may arise the problem that the safe operating area (hereafter, the SOA) of the MOSFET decreases on the high voltage side, as shown by the ◯ marks in FIGS. 4 and 5. FIGS. 4 and 5 are Vds-Id characteristic diagrams showing SOAs of MOSFETs with a rated voltage of 250V and a rated current of 13 A in FIG. 4 and of 42 A in FIG. 5. FIG. 4 corresponds to the MOSFET of FIG. 13A, and FIG. 5 corresponds to the MOSFET of FIG. 13B.
For example, it is found when comparing 20V and 250V in FIG. 4 that the SOA decreases in power from 1000 W to 750 W, while it is found from a comparison of 10V and 250V in FIG. 5 that the SOA decreases in power from 1000 W to 125 W.
A more detailed description will be given of the previously described problem. It is conceivable that the reason for the SOA decreasing in this way is that local heat generation is occurring in a device chip, as in FIG. 6 (an MOSFET rated at 250V and 13 A) and FIG. 7 (an MOSFET rated at 250V and 42 A), each showing a generated heat distribution in the saturation region of a heretofore known MOSFET, the miniaturization of the cell structure (cell pattern) of which has been carried out. FIGS. 6 and 7 are top views of resin seal type (package type: TO220) MOSFETs corresponding to FIGS. 4 and 5, respectively, each showing a condition in which heat is generated in the saturation region when energizing. In each of FIGS. 6 and 7, a design of a heat-generated condition of an MOSFET chip is made, excluding a seal resin, as well as region portions high in generated heat temperature being shaded in such away as to look darker as the temperature increases. Temperature ranges corresponding to the respective shadings are described in FIGS. 6 and 7. It can bee seen in a comparison of FIGS. 6 and 7 that the high heat generation regions in FIG. 6 are wider than those in FIG. 7. The names of elements of the semiconductor device (the MOSFET chip, a gate terminal, a drain terminal, a source terminal, source and gate connecting wires, a metal frame, and the like) are described for reference in each of the top views of FIGS. 6 and 7.
The reason that this kind of local heat generation occurs in the MOSFET chip will be described referring to diagrams of FIGS. 8 and 9, each representing a relationship between a channel conductance Gd (the gradient of a drain-source current Id) to agate voltage Vg of an MOSFET and temperature characteristics. FIG. 8 corresponds to the MOSFET of FIG. 6, and FIG. 9 corresponds to the MOSFET of FIG. 7.
Each forward transfer characteristic diagram (FIGS. 8 and 9) is obtained by combining the dependence of the gate threshold voltage Vth and carrier mobility on temperature (junction temperature) and the dependence of the drain-source current (Id) (hereafter abbreviated simply to the current (Id)) of each MOSFET device on the gate voltage (Vg). That is, each of these characteristic diagrams is such that the amounts of current (Id) flowing through the channel of the MOSFET at a predetermined gate voltage Vg are plotted with respect to the gate voltage (Vg) with different temperatures (junction temperatures) as parameters. In general, the channel conductance (Gd) (the gradient of this curved line) decreases with the temperature. Each of FIGS. 8 and 9 shows that a plurality of plot lines formed by the different temperatures cross through one point. The point at which the plurality of Id-Vg curved lines cross is called a cross point.
In the region of the current (Id) and Vg below the cross point, Id further increases with a rise in temperature with respect to a constant Vg (a positive temperature coefficient). For example, a certain portion of the MOSFET, that is, one unit cell or a plurality of adjacent cells are considered. Herein, the cell is the unit of MOSFET including one gate, and for example, FIG. 1 shows a half of the cell. In the region of Id or Vg below the cross point, when the current concentrates on a specific portion for some reason, the temperature (junction temperature) in the portion rises. Then, the current in the portion increases because the Id-Vg characteristics have the positive temperature coefficient when the gate voltage is constant. As a result of this, more current is caused to concentrate on the specific portion, meaning that positive feedback acts on Id, and a current operation of the MOSFET becomes unstable with a rise in temperature.
Meanwhile, in the region of Id or Vg below the cross point, Id decreases with a rise in temperature with respect to a constant Vg (a negative temperature coefficient). Because of this, even though the current concentrates on a certain portion, and the temperature rises in the certain portion, the current in the portion decreases, meaning that negative feedback acts on Id. As a result of this, the current operation of the MOSFET remains stable despite a rise in temperature.
A description will be given of the unstability of an operation in the region of Id and Vg below the cross point. In the case of the operation below the cross point, the gate threshold voltage (Vth) drops when the temperature of a local region of the device chip rises due to some problem with a wafer process or to packaging heterogeneity. When the gate threshold voltage (Vth) drops, a gate drive becomes stronger, thus raising the current (Id). More heat is generated in the local region due to the rising current (Id), and the gate threshold voltage (Vth) further drops. The positive feedback occurs in this way, thus resulting in a failure or breakdown due to hot spotting and eventually to thermal runaway or the like of the device.
FIG. 9 shows a forward transfer characteristic diagram of the heretofore known MOSFET device (FIG. 13B) whose cell pattern is still more miniaturized than in FIG. 8. As shown in FIG. 8 (the MOSFET rated at 250V and 13 A) and FIG. 9 (the MOSFET rated at 250V and 42 A), it can be seen that the “positive” temperature coefficient region (the region below the cross point) of FIG. 9 is wider than that of FIG. 8 as the cell pattern of the device chip is more miniaturized.
The gate threshold voltage (Vth) naturally varies even in one device, and the drain-source current (Id) (hereafter, the current (Id)) starts to flow from a portion in which the gate threshold voltage (Vth) is lowest. By the current (Id) flowing locally in this way, heat is generated in this local area, but when the temperature coefficient of the channel conductance is positive at this time, it is easier for the current to flow, and the current concentrates, due to which the SOA decreases. Conversely, when the temperature coefficient is negative, it is difficult for the current (Id) to flow as a result of a rise in temperature, and the current (Id) is uniformized in the device. It is conceivable that, as a result of this, a wide SOA appropriate for the size of the device is secured in order to cause the current (Id) to flow uniformly in the whole of the device.
However, with only a simple cell pattern miniaturization such as the previously described miniaturization from FIG. 13A to FIG. 13B, when the on-resistance (Ron) decreases, the SOA also decreases (deteriorates) at the same time. Therefore, there arises a new problem in that the trade-off between the on-resistance (Ron) and SOA becomes obvious, as previously described.